The present invention relates to improved layout and operating schemes for integrated circuit dynamic random access memories.
In the design of sense amplifiers for dynamic random access memories (DRAMs), a common technique referred to as folded bit lines is used to increase the signal to noise ratio. In that scheme, the small voltage to be sensed is developed between two parallel bit lines. The purpose behind such scheme is to minimize any differential signal presented to the sense amps by noise or process variations. By laying the bit lines close together and matching them geometrically, most noise will be seen by the sense amp as a common mode signal. Since the sense amps are designed to detect differential voltages, such common mode noise signals do not affect the reading of data.
A key circumstance which allows the implementation of such a folded bit line approach is the ability to run two word lines within one memory cell pitch. Only one memory cell's charge can be sensed on a single bit line. The two parallel bit lines are each generally considered to be half of a bit line, and only one bit of data can be sensed per whole bit line. Because the bit line is folded into two parallel half bit lines, adjacent cells on the separate halves of a bit line must be addressed by separate word lines. Such an addressing scheme is shown in FIG. 1. If the memory cell size is shrunk below twice the word line pitch, either the folded bit line scheme cannot be used or unused blank area must be left within the memory cell array.
It is therefore an object of the present invention to provide an improved layout and signal connection scheme whereby differential sensing such as found in folded bit lines can be used with small memory cells. It is another object of the present invention to improve the packing density of large arrays of small memory cells.
Therefore, in accordance with the present invention, two parallel bit lines have differential sense amplifiers on both ends. Adjacent memory cells on the parallel bit lines are addressed by a single word line. Both bit lines are electrically broken by pass transistors, so that one bit line couples one memory cell to one sense amp, and the other bit line couples the other memory cell to the other sense amp. Using this scheme, two bits are accessed by a single word line. In order to decrease undesirable capacitances, memory cells may be grouped into segments which are selectively coupled to the bit lines. Only the segment containing the selected memory cell is coupled to the bitline when that cell is read, so that only the capacitance of one segment line plus the bit line is presented to the sense amplifier. A repetitive linear pattern of bit lines and sense amps allows each sense amp to detect signals from bit lines on either side, although not simultaneously.
In order to more accurately balance the impedances presented to the sense amps, a segment in a currently non-selected portion of the array can be coupled to a sense amp to balance the impedance of a selected segment containing the selected memory cell.
In order to reduce differential mode noise signals caused by stray capacitances between crossing signal lines, the various select transistors should be selected in a controlled pattern.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereinafter appear, and for purposes of illustration, but not of limitation, several preferred embodiments are shown in the accompanying drawings.